1. Field of the Invention
The present invention relates generally to module cell generating device of semiconductor integrated circuits, and more particularly, to a module cell generating device for generating layout designing data.
2. Description of the Background Art
In the semiconductor integrated circuit, there is a region called a module cell having regular layout structure such as a RAM, a ROM, a PLA, and a multiplier. In designing process of the semiconductor integrated circuit, a method of designing such a module cell is carried out by using a basic cell arranging and wiring device referred to as a module cell generating device. The module cell generating device automatically designs the layout of the module cell by providing a designation parameter characterizing each of the module cells when designing them. FIG. 10 is a system configuration diagram of the module cell generating device. Referring to FIG. 10, a conventional module cell generating device comprises a parameter input part 1, a module cell generating process part 2, and a layout designing data output part 3.
Parameter input part 1 applies a designation parameter 1a necessary for the generation of the module cell. The typical parameter, for example, is the bit number of 1 word, storage capacity, or the magnitude of the layout of module cell in the module cell of RAM.
Module cell generating process part 2 comprises a basic cell group 21, a structure description part 22, and a basic cell arranging and wiring process part 23. Basic cell group 21 stores various basic cells. The basic cell is fundamental layout designing data for constructing layout designing data. A specific example of the basic cell will be described. FIG. 11 shows a basic cell structure diagram showing one example of the basic cell showing wiring structure. A basic cell 30 has two wirings 31 and 32. FIG. 12 is a structure diagram of another basic cell. A basic cell 40 comprises one transistor, a source wiring 41, a drain wiring 42, and a gate wiring 43. FIG. 12 shows the circuit diagram of the basic cell shown in FIG. 13. FIG. 13 shows a transistor 51, a source 5S, a drain 5D, a gate 5G corresponding to source wiring 41, drain wiring 42, and gate wiring 43 of the basic cell shown in FIG. 12, respectively.
In structure description part 22, structure description including designation and arrangement direction repeating numbers of the basic cells used, relationship between the basic cells, and the wiring of the basic cells is programmed. Furthermore, structure description which describes about how they change in response to the designation parameter is programmed. Structure description part 22 provides various designations as mentioned above to basic cell arranging and wiring process part 23.
Basic cell arranging and wiring process part 23 generates layout designing data of the module cell in response to the basic cell applied from basic cell group 21, the structure description from structure description part 22, and designation parameter 1a applied from parameter input part 1 to provide the generated layout designing data to layout generating data output part 3.
The operation of a conventional module cell generating device will be described with reference to three examples. Generation of layout designing data shown in FIGS. 14, 15, and 16 using basic cell 30 shown in FIG. 11 and basic cell 40 shown in FIG. 12 will be described.
Let us assume that X, Y, and Z are applied as the designation parameter from parameter input part 1 at first. Let us also assume that "Basic cell 40 is arranged to Y side of a basic cell X by moving it upward for Z" is programmed in structure description part 22.
Under the condition described above, in the first example shown in FIG. 14, X=1, Y=right, and Z=0 are applied as the designation parameter. Basic cell arranging and wiring process part 23 fetches basic cell 30 and basic cell 40 from basic cell group 21, implementing layout design in accordance with designation parameter 1a and structure description 22 to provide layout designing data of the pattern shown in FIG. 14 to layout designing data output part 3. The layout shown in FIG. 14 extends a source line 41 of the transistor of basic cell 40 by wiring 31 of basic cell 30, and also a gate wiring 43 by wiring 32.
In the second example shown in FIG. 15, X=1, Y=right, and Z=1/2 are applied as the designation parameter. Layout designing data shown in FIG. 15 is generated in accordance with the designation parameter, the structure description, and the basic cell. In the layout shown in FIG. 15, gate wiring 43 of the transistor of basic cell 40 is extended to wiring 31 of basic cell 30, and wiring 32 is not connected to anywhere.
In the third example shown in FIG. 16, X=2, Y=right, and Z=0 are applied as the designation parameter. Layout designing data of FIG. 16 is generated in accordance with the designation parameter, the basic cell, and the structure description. In the layout shown in FIG. 16, the gate wirings of the left and right basic cells 40 are connected by generating the same form of basic cell 40 on the right side of basic cell 40, and drain wiring 42 of the left side basic cell 40 is connected to source wiring 41 of the right side of basic cell 40. A circuit diagram corresponding to FIG. 16 is shown in FIG. 17.
As mentioned above, the conventional module generating device can automatically generate layout designing data in accordance with designation parameter la, basic cell group 21, and structure description 22.
However, in the conventional module cell generating device, basic cell group 21 was constituted only by the basic cells provided with their form fixed in advance. Therefore, there was a limit to layout designing data of the semiconductor integrated circuit which can be generated by the combination of these basic cells. This means that the layout designing data in combination with the basic cell not included in basic cell group 21 was not generated. In other words, in order to generate such layout designing data, the operation of storing the basic cell after creating it intentionally in basic cell group 21 was necessary for the device in addition to automatical designing operation of the module cell generating device in advance. These operations are not preferable because the number of process steps of designing operation is increased and make them more complicated.